Analog circuit performance can be adversely affected by supply noise of a voltage source. To reduce the noise associated with the voltage signal, filter networks have been utilized. However, care must be taken to ensure that the filter networks necessary to reduce the noise does not decrease the supply voltage to unusable levels.
Attempts have been made to minimize the effects of supply noise on sensitive analog circuits by arranging a filtering network next to silicon. Moreover, filtering can be arranged at board, package or die, whereby a filtered supply voltage is applied to the analog circuit.
The most effective filters have low cut-off frequencies, i.e., high RC value for traditional RC low-pass filters. However, a high resistance value induces excessive IR drop, such that a voltage sufficient for operating the circuit is not supplied, which can result in performance degradation or inoperability.
Managing integrated passive filter components for negligible IR drop does not provide optimal filtering of low frequency noise. These filters produce some attenuation but noise remaining after filtering can still be too great. An RC network is shown in FIG. 1, where AVdd is the supply voltage and AVdd_RC is the filtered supply. C is an intrinsic analog supply capacitance to ground, e.g., an N-well to substrate parasitic capacitance, and can be, e.g., 100 pF, and R is composed of a typical package and die wiring, which can be, e.g., 5 Ω. For the instant example, it is assumed that the minimum tolerable voltage for the analog circuit is 1.4V, such that supply voltage AVdd is selected to be, e.g., 1.5 V. However, supply voltage AVdd, shown in the left-hand graph, also includes peak-to-peak noise of 400 mV. Thus, when supply voltage AVdd is filtered through the RC network, the expected voltage loss through the network produces an acceptable average voltage of, e.g., 1.45 V, see right-hand graph. However, the peak-to-peak noise of 90 mV applied to the analog circuit remains too high and may degrade performance.
As R is increased in known filtering; effective noise filtering is achieved through a reduced filter bandwidth, however, filtered supply AVdd_RC is also reduced to unusable levels. The RC network shown in FIG. 2, where C again is an intrinsic analog supply capacitance to ground, e.g., an N-well substrate, and can be, e.g., 100 pF. However, R is increased for maximum cut-off frequency to provide sufficient noise filtering, e.g., 33 Ω. As with the previous example of FIG. 1, it is assumed that the minimum tolerable voltage for the analog circuit is 1.4V, such that the supply voltage AVdd of, e.g., 1.5 V with peak-to-peak noise of 400 mV, is utilized, see left-hand graph. Thus, when supply voltage AVdd is filtered through the RC network, the noise amplitude is reduced by three times to, e.g., 30 mV. However, as shown in the right-hand graph of FIG. 1, the average filtered signal AVdd_RC of, e.g., 1.17 V is too low for operating the analog circuit.
To avoid the above-noted drawbacks of the filter networks, a voltage regulator, e.g., a linear regulator or a switched regulator, has been employed for analog supply creation. As shown in FIG. 3, a regulator 10 supplies a supply voltage AVdd to an analog circuit 20. Regulator 10 can be formed by a generator 11 supplying a reference voltage Vref, which is the nominal AVdd required by analog circuit 20. Reference voltage Vref and supply voltage AVdd are input to an operational amplifier 12. The output of operational amplifier 12 is coupled to supply AVdd to analog circuit 20 through field effect transistor (FET) 13. A supply voltage AVcc, which is somewhat higher than AVdd, is applied to FET 13, operational amplifier 12, and generator 11. While this solution provides sufficient voltage for operating analog circuit 20, the solution does not sufficiently reduce noise in the supply signal, AVdd.
To address the noted deficiency in the voltage regulator solution, an RC filtering network 15, shown in FIG. 4, is provided to filter AVdd to supply filtered signal AVdd_RC to analog circuit 20. Moreover, it is noted that filtered signal AVdd_RC is fed back to operational amplifier 12, which also receives as an input a signal from Vref generator 11. Thus, the maximum available IR drop becomes AVdd−Avdd_RC. Further, filter network 15 utilizes the intrinsic capacitance of the chip structure, due to n-well, nFETs, etc., which is represented as capacitor 17. However, this arrangement does not allow noise filtering to be maximized.